Method for manufacturing semiconductor device

ABSTRACT

According to the present invention, a process for changing the form of a processed film is performed to planarize it before the processed film which is formed on a wafer is processed in a manufacturing process of a semiconductor device. As the process for changing the form of the processed film, there may be exemplified a single wafer type wet etching process. The compatibility of the processed film with processing means is taken into consideration and, for instance, the wet etching process is applied to the processed film so as to eliminate parts incompatible with the processing means, so that a distribution in-plane of the processed film is previously improved.

TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing asemiconductor device, and more particularly to a technology that theform of a processed film is previously adapted to an optimum form inaccordance with the feature of a processing method.

BACKGROUND ART

[0002] In recent years, the submicron feature and the formation of themulti-layers of devices or wirings have been advanced with the highintegration of a semiconductor device. While the submicron patterns ofwirings have been formed by a thin film forming technology and alithography technology, it is essentially necessary, upon formation ofthe multi-layers, to planarize a surface for the purpose of forming thesubmicron patterns with good accuracy. For instance, the submicronfeature of a gate electrode greatly depends on the performance of theexposure device of the lithography technology. However, as for thesubmicron feature of a device isolation area and the reduction ofdistance from the gate electrode, the planarization technology of asubstrate according to a Shallow Trench Isolation (refer it to as toSTI, hereinafter) technology as well as a lithography technology alsoattracts attention.

[0003] As for the device isolation technology of LSI, an LOCOS isolationtechnology by a thermal oxide film has been hitherto employed. In theLOCOS, since an Si₃N₄ film is used as a mask to thermally oxidize an Sisubstrate itself, there exist great advantages that a process is simpleand problems due to the device stress of the oxide film are rarelygenerated and the quality of the produced oxide film is good. Therefore,also in an LSI process in which a technological innovation is ardentlycarried out, an improvement is continuously performed in to the LOCOSisolation technology and the improved LOCOS isolation technology hasbeen continuously used. However, as the generation of 0.25 μm occupiesthe main current, the LOCOS begins to arise a limitation from theviewpoint of submicron feature.

[0004] More specifically explained, a device isolation pitch isundesirably widened more by the approach of, what is called a bird'speak than the width of an opening of the Si₃N₄ film as the mask due tothe bird's peak in which an oxidation reaction is spread in a transversedirection upon thermal oxidation. In order to suppress the bird's peak,a method for deleting a pad oxide film located just below the Si₃N₄ filmmay be effectively used, however, stress on the Si substrate by theSi₃N₄ film inconveniently causes the defect of crystal to be generated.

[0005] As described above, when the LOCOS is viewed from all-roundaspects, the bird's peak becomes fatal so that it must be said that thesubmicron feature of the LOCOS is very difficult. Thus, as the deviceisolation technology, the STI is paid attention to in place of theLOCOS. According to the STI, since trenches are etched to fillinsulating materials therein, there exists less conversion differencefrom a design dimension, and accordingly, the STI is suitable for thesubmicron manufacturing in principle. Further, since a surfaceplanarizing operation is carried out by any method as described belowafter the insulating materials are filled in the trenches, the STI isadvantageous in view of flatness required for highly accuratelithography.

[0006] The above described planarization technology is employed not onlyfor the device isolation, but also for planarizing insulating filmsbetween wiring layers. Therefore, under these circumstances, asemiconductor device of next generation may not be established withoutthe planarization technology.

[0007] As described above, the planarization technology essentiallyneeds to be applied to a device of new generation. However, in recentyears, a CMP (chemical mechanical polishing) technology has beenordinarily employed. An example in which the CMP technology is appliedto the device isolation technology is shown in FIG. 10.

[0008]FIG. 10 shows a state in which trenches 102 are formed on asilicon substrates 101 and a filled insulating film 104 is filledtherein by a CVD method. An S₃N₄ film 103 is used as a CMP stopper layerto polish the filled insulating film 104 by employing a polishingmaterial including silica as a main component from the state shown inFIG. 10.

[0009] The filled insulating film 104 used in this case is ordinarilyformed by the plasma CVD method. However, according to the feature ofthe plasma CVD method, the film thickness t₂ of the outer peripheralpart of a wafer is apt to be inevitably larger than the film thicknesst₁ of the central part of the wafer (see FIG. 10).

[0010] In case that the CMP polishing is carried out from this state,when CMP polishing conditions are set on the basis of the film thicknessof the central part of the wafer, the filled insulating film 104 on theSi₃N₄ film serving as the CMP stopper layer will not be polished andremain in the peripheral part of the wafer as shown in FIG. 11.

[0011] While this state is maintained, when the Si₃N₄ film as thestopper layer is to be removed by a wet etching method using hotphosphoric acid or an isotropic chemical dry etching method in a nextstep, the filled insulating film 104 remaining in the peripheral part ofthe wafer becomes a mask so that the film cannot be clearly removed. Asa result, a desired processed form cannot be obtained in the peripheralpart of the wafer so that the semiconductor device is inferior in viewof characteristics, which causes a yield to be deteriorated.

[0012] For avoiding the above described adverse influences, when thefilled insulating film 104 on the Si₃N₄ film 103 in the outer peripheralpart of the wafer is to be polished so that the filled insulating film104 is not left, the filled insulating film 104 in the trench 102 at thecentral part of the wafer is excessively polished next time. Thus, asshown in FIG. 12, the thickness of the filled insulating film 104 in thetrench 102 at the central part of the wafer is different from that inthe outer peripheral part.

[0013] At this time, there is not generated a problem in removing theSi₃N₄ film 103 as the stopper layer in a next step, however, since thefilm thickness of the filled insulating film 104 in the trench 102 isdifferent between that of the central part of the wafer and that of theouter peripheral part of the wafer, a device isolation feature isconsequently different in the surface of the wafer. Therefore, thedesired characteristics of the semiconductor device cannot be obtainedto cause a yield to be deteriorated.

[0014] Under these circumstances, a CMP planarization technology inwhich the processed film irrespective of the thickness of the processedfilm in the wafer is examined, however, desired results cannot bepresently obtained.

DISCLOSURE OF THE INVENTION

[0015] The present invention was proposed by taking the above-describedactual conditions into consideration and it is an object to provide amethod for manufacturing a semiconductor device which can eliminateunevenness in characteristics due to the thickness distribution of aprocessed film and a performance difference as a problem resultingtherefrom.

[0016] The inventors of the present invention eagerly studied to achievethe above-described object, so that they found that, before theprocessed film is processed, the distribution in-plane of the thicknessof the processed film is preferably previously improved.

[0017] The present invention was completed on the basis of thisknowledge, it is an object to provide a method for a semiconductordevice wherein a process for previously changing the form of a processedfilm is performed to planarize it before the processed film which isformed on a wafer is processed in a manufacturing process of thesemiconductor device.

[0018] According to the present invention, the distribution in-plane ofthe processed film is previously improved by taking into considerationthe compatibility of the processed film with processing means andapplying, for instance, a wet etching process to the processed film soas to cancel a part incompatible therewith.

[0019] As described above, since only the part incompatible with theprocessing means is removed by the wet etching method, what is called “afilm thickness correcting wet etching technology” may be applied, sothat subsequent processing works can be uniformly carried out toeliminate unevenness in characteristics of a semiconductor device.

[0020] Still other objects of the present invention and the specificadvantages obtained by the present invention will become more apparentfrom the description of embodiments described below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a schematic view showing one example of a dischargingmethod for etchant chemical.

[0022]FIG. 2 is a schematic view showing another example of adischarging method for etchant chemical.

[0023]FIG. 3 is a schematic view showing a state in which a filled oxidefilm is formed.

[0024]FIG. 4 is a characteristic view showing the profiles of thethickness of the filled oxide film.

[0025]FIG. 5 is a schematic view showing the state of a filled oxidefilm after a wet etching process.

[0026]FIG. 6 is a schematic view showing the state of the filled oxidefilm after a CMP process.

[0027]FIG. 7 is a schematic view showing a state in which an interlayerinsulating film is formed.

[0028]FIG. 8 is a schematic view showing the state of the interlayerinsulating layer after the wet etching process.

[0029]FIG. 9 is a schematic view showing the state of the interlayerinsulating film after the CMP process.

[0030]FIG. 10 is a schematic view showing a state in which a filledoxide film is formed.

[0031]FIG. 11 is a schematic view showing the state of the filled oxidefilm after the CMP process when the CMP polishing conditions are set tomeet the central part of the wafer.

[0032]FIG. 12 is a schematic view showing the state of the filled oxidefilm after the CMP process when the CMP polishing conditions are set tomeet the peripheral part of the wafer.

BEST MODE FOR CARRYING OUT THE INVENTION

[0033] Now, a method for manufacturing a semiconductor device to whichthe present invention is applied will be described in detail byreferring to the accompanying drawings.

[0034] The method for manufacturing a semi conductor device according tothe present invention is based on a fundamental conception that theprofile of the thickness of a processed film is previously grasped, and,for instance, etchant chemical is discharged only to parts incompatiblewith processing means such as parts with large film thickness to etchthem. A single wafer type wet etching method is most suitably employedfor the above-described etching.

[0035] In order to etch only the above-described parts with the largefilm thickness, etchant is discharged to many points on the basis of,for instance, positional information in the radial direction of a waferand film thickness profile information.

[0036] Specifically, as shown in FIG. 1, a wafer 1 is rotated. While achemical nozzle 2 is moved from an outer peripheral side to a centralside, etchant chemical 3 is discharged to etch a processed film on thewafer 1.

[0037] In the processed film which is formed on the wafer 1, thethickness of the outer peripheral side of the wafer 1 is ordinarilyliable to be larger than that of the inner peripheral side.

[0038] As described above, when the etchant chemical is discharged fromthe chemical nozzle 2 while the wafer 1 is rotated, the chemical flowsoutward in accordance with a centrifugal force like, what is called aspin coater or the like.

[0039] Here, when the etchant chemical 3 is sequentially dischargedwhile the chemical nozzle 2 is moved from the outer peripheral side tothe central side, the outer peripheral side is exposed the more by theetchant chemical 3 for a long time. In other words, the processed filmin the outer peripheral side is etched the more for a long time so thatthe amount of etching is increased. Thus, the difference in thethickness of the processed film between the outer peripheral side andthe inner peripheral side is canceled.

[0040] At the time of the above-described wet etching process, asetchant chemical, a kind of chemical capable of etching a processed filmin a lower etching rate is preferably employed. When an etching rate istoo high, it is difficult to control the amount of etching, whichundesirably leads to excessive etching.

[0041] Further, the discharge of the chemical at the specific positionof the wafer is preferably set to a small flow rate, a short-timeprocess and the rotating speed of the wafer under which the chemicaldoes not flow to a central direction. When the etchant chemical flows tothe inner peripheral side, this makes it difficult to eliminate thedifference in film thickness.

[0042] As mentioned above, this technology is employed so that thethickness distribution of the processed film can be previously uniformlyset. Thus, the above-described problems can be avoided by processing thefilm under, for instance, the CMP process.

[0043] By the way, when the etchant chemical is continuously dischargedfrom the central direction of the wafer, the processed film may bepossibly inevitably urged to be etched too much in an edge direction. Inorder to avoid this phenomenon, the temperature of the etchant chemicalis controlled to high temperature, for instance, to 30° C. or higher,preferably to 40° C. to 60° C. so that the amount of etching ispreferably suppressed in accordance with a cooling effect when theetchant chemical flows to a part in the periphery of the wafer.

[0044] When the temperature of the etchant chemical is higher, theetching rate is the higher. As shown in FIG. 2, when the hightemperature etchant chemical 3 is discharged from the chemical nozzle 2,the etching rate is high in the vicinity of the discharge position.Then, as the etchant chemical flows to the outer peripheral side, thetemperature of the etchant chemical 3 is gradually lowered so that anetching rate is also gradually lowered. Thus, the etching rate isgreatly lowered in the outer peripheral edge of the wafer 1.Accordingly, the excessive etching of the processed film is prevented inthe edge of the wafer 1.

[0045] When the above-described method is employed, a function forlowering the temperature of the peripheral part of the wafer 1 is moreeffectively utilized in order to urge the etchant chemical to be cooled.As a mechanism for applying the function for lowering the temperature,for instance, there may be exemplified a measure for discharging N₂ onlyto the back surface of the peripheral part of the wafer 1 to cool it.

[0046] The addition of this technique makes it possible to previouslyobtain an ideal thickness distribution of the processed film. Then, thefilm is processed by the CMP process or the like so that theabove-described problem can be avoided.

[0047] The above-described high temperature etchant chemical is put topractical use so as to meet, for instance, a case in which the thicknessof the processed film in the inner peripheral side of the wafer 1 islarger than that in the outer peripheral side.

[0048] As described before, when the high temperature etchant chemicalis discharged, the etching rate in the vicinity of a chemical dischargeposition is higher than the etching rate in a position separatetherefrom.

[0049] Therefore, in case that the thickness of the processed film inthe inner peripheral side of the wafer 1 is larger than that in theouter peripheral side, when the high temperature etchant chemical isdischarged to the inner peripheral position in which the thickness ofthe processed film is larger, the inner peripheral side is etched in ahigher etching rate and the outer peripheral side is etched in a loweretching rate. As a result, the amount of etching in the inner peripheralside is larger than that in the outer peripheral side to correct thefilm thickness difference.

[0050] The present invention can be also applied to, for instance, aninsulating film planarizing CMP between wiring layers, a metallic filmfilling CMP, etc. as well as the CMP technology of the device isolation.Further, the present invention may be applied to an etching back methodas a planarization technology except the CMP, an ITO film or a spreadfilm or the like. In addition, the present invention can be applied tothe improvement of in-plane unevenness in a dry etching process.

EXAMPLES

[0051] Now, specific examples of a method for manufacturing asemiconductor device to which the present invention is applied will bedescribed in accordance with experimental results.

Example 1

[0052] A sample used in this example has a structure shown in FIG. 3. Ona silicon substrate 11, a thermal oxide film 12 of the thickness ofabout 5 to 20 nm and a silicon nitride film as a CMP stopper film 13 ofthe thickness of about 50 to 250 nm were previously formed in accordancewith a pressure reducing CVD method, then, a photoresist was patternedby a KrF excimer stepper to form trenches 14 with the depth of 450 nm. Asilicon oxide film 15 was accumulated thereon as a filled film by a CVDmethod.

[0053] At this time, the thickness of the filled oxide film 15 on thestopper film 13 was measured in the radial direction of a wafer toobtain a profile before a wet etching process as shown in FIG. 4. Asunderstood from the figure, there exists a large film thicknessdifference between the film thickness T₁ of the central part of thewafer and the film thickness T₂, of an outer peripheral part.

[0054] In order to cancel the thickness of the outer peripheral part forthe above-described profile, a single wafer type wet etching process wasapplied to the wafer. In the present example, the structure shown inFIG. 3 was processed under conditions described below. 1) As chemicalwhich can wet-etch the filled oxide film 15 as the processed film,dilute hydrofluoric acid (DHF) is employed, 2) In order to suppressetching in an outermost peripheral part, the temperature of the chemicalis set to high temperature (about 50° C.) and N₂ is discharged from theback side of the wafer to enhance the cooling effect of the substrate,3) A nozzle for discharging the chemical from the position 80 mm spacedfrom a center to 30 mm inward in the steps of 5 mm is moved as shown inFIGS. 1 and 4) One step of atomization of the chemical is carried outfor 2 to 4 seconds and the flow rate of discharge is set to low flowrate as low as 1 liter/minute or less.

[0055] The thickness of the filled oxide film 15 on the stopper film 13obtained after the above-described process was carried out was measuredin the radial direction of the wafer to have a profile after the wetetching process as shown in FIG. 4. As understood from FIG. 4, thethickness of the filled oxide film 15 in the outer peripheral part isreduced and the substantially same thickness is obtained from the centerto the outer peripheral side (see FIG. 5).

[0056] All the filled film 15 located on the stopper layer 13 ispolished in accordance with the CMP technology and removed from thisstate. Since there is no difference in form between the central part andthe outer peripheral part of the wafer, the device isolation structuresof the completely same form can be achieved in all the plane of thewafer, as shown in FIG. 6.

Example 2

[0057] A sample used in this example has a structure shown in FIG. 7. Inthis sample, a metallic wiring film is formed on an oxide film 21 inwhich a semiconductor is formed, and further, the film is processed andpatterned in accordance with a lithography technique and a reactive ionetching (RIE) technique to form metallic wirings 22. Then, an interlayerinsulating film 23 between the wiring layers is formed by the CVDmethod. When a plasma CVD method is used for the CVD method, the form inthe plane of a wafer is formed so that the thickness of the film in acentral part is different from that in a peripheral part. Thus, thesectional structure in the plane of the wafer is different as shown inFIG. 7.

[0058] In order to cancel the thickness of the outer peripheral part forthe above described form, a single wafer type wet etching process isapplied to the wafer. In this example, the structure shown in FIG. 7 wasprocessed under conditions described below. 1) As chemical which canwet-etch the interlayer insulating film 23 as the processed film, dilutehydrofluoric acid (DHF) is employed, 2) In order to suppress etching inan outermost peripheral part, the temperature of the chemical is set tohigh temperature (about 50° C.) and N₂ is discharged from the back sideof the wafer to enhance the cooling effect of the substrate, 3) A nozzlefor discharging the chemical from the position 80 mm spaced from acenter to 30 mm inward in the steps of 5 mm is moved as shown in FIGS. 1and 4) One step of atomization of the chemical is carried out for 2 to 4seconds and the flow rate of discharge is set to low flow rate as low as1 liter/minute or less.

[0059] The form of the interlayer insulating film 23 obtained after theabove-described process is performed is shown in FIG. 8. The form of thecentral part of the wafer is substantially the same as that of the outerperipheral part. As apparent from the figure, the thickness of theinterlayer insulating film 23 is reduced to have the substantially equalthickness from the center to the outer periphery.

[0060] On the other hand, a result obtained by planarizing theinterlayer insulating film 23 using the CMP technique or using theetching back method by RIE technique is shown in FIG. 9. As understoodfrom FIG. 9, there is not present a difference in form between thecentral part and the outer peripheral part of the wafer so thatstructures between wiring layers having the same form can be achieved inall parts in the plane of the wafer.

[0061] In the above-described examples, although there is disclosedexamples in which the process for previously changing the form of theprocessed film is applied to the processed film which is formed on thewafer, for instance, the filled silicon oxide film to planarize itbefore a processing work, the processed film may be the wafer itself.For example, when the thickness of the central part of the wafer isdifferent from that of the outer peripheral part thereof, the wafer maybe planarized by using the method of the present invention.

[0062] Industrial Applicability

[0063] As described above, according to the present invention, since thein-plane distribution of the processed film is previously improved so asto meet the characteristics of the processing method, before theprocessing of the processed film, for instance, the chemical mechanicalpolishing (CMP) method or the reactive ion dry etching (RIE) method iscarried out, the performance difference such as the unevenness incharacteristics of the semiconductor device can be canceled, which cancontribute to the improvement of yield or the like.

1. A method for a semiconductor device, wherein a process for previouslychanging the form of a processed film is performed to planarize itbefore the processed film which is formed on a wafer is processed in amanufacturing process of the semiconductor device.
 2. The method formanufacturing a semiconductor device according to claim 1, wherein theprocess for changing the form of the processed film is a wet etchingprocess.
 3. The method for manufacturing a semiconductor deviceaccording to claim 2, wherein the wet etching process is a single wafertype wet etching process.
 4. The method for manufacturing asemiconductor device according to claim 2, wherein a profile of thethickness of the processed film is previously grasped and the wetetching process is performed in accordance with it.
 5. The method formanufacturing a semiconductor device according to claim 4, whereinetchant chemical is discharged only to the thick parts of the processedfilm.
 6. The method for manufacturing a semiconductor device accordingto claim 4, wherein the etchant chemical is discharged to many points inthe radial direction of the wafer while the wafer is rotated on thebasis of the thickness profile information of the processed film in theradial direction of the wafer.
 7. The method for manufacturing asemiconductor device according to claim 4, wherein the temperature ofthe etchant chemical is set to high temperature and the amount ofetching is controlled in accordance with a cooling effect when theetchant chemical flows.
 8. The method for manufacturing a semiconductordevice according to claim 7, wherein the temperature of the wafer isselectively lowered to urge the etchant chemical to be cooled.
 9. Themethod for manufacturing a semiconductor device according to claim 8,wherein N₂ or cooling air is sprayed to the back surface of the wafer tolower the temperature of the wafer.
 10. The method for manufacturing asemiconductor device according to claim 2, wherein the processed film isa silicon oxide film and hydrofluoric acid is used as the etchantchemical liquid for the wet etching process.